1. Field of the Invention
The present invention relates to a transconductance-capacitance filter, and a method of verifying transfer characteristics in a transconductance-capacitance filter. More particularly, the present invention relates to a transconductance-capacitance filter, and a method of verifying the transfer characteristic of a high-frequency integrated continuous-time filter of a transconductance-capacitance (gm-C) type.
2. Description of the Background Art
The four basic linear operations (integration, scaling, summation, inversion) used to synthesize a large class of transfer functions can be easily implemented using only transconductors and capacitors. For example, a transconductor loaded with a capacitor acts as a voltage inputxe2x80x94voltage output integrator. Scaling is done by changing the transconductance of the transconductor and/or the capacitance of the load capacitor. The output currents of a plurality of transconductors can be summed by tying the outputs to a same node. Also, inversion can be done for instance by crossing inputs of a transconductor.
The basic building block of a transconductance-capacitance filter is a multiple input transconductance-capacitance integrator. This block can perform all of the above noted basic operations. The filter appears as a collection of interconnected multiple input transconductance-capacitance integrators. In an integrated circuit, both the transconductance of the transconductor and the capacitance of the capacitor are subject to influences such as fabrication processes, power supply and temperature variations. Thus, it is required to check the conformity of the implemented transfer function and to tune the filter so as to fulfill the designed function. Most of the tuning effort is directed toward adjusting the transconductance of the transconductors.
One of the conventional direct methods of checking the transfer function of a continuous-time filter consists of applying a constant amplitude, variable (sweeping) frequency sinusoidal signal at the input of the filter and measuring the amplitude and the phase of the resulting waveform at the output of the filter. Indirect methods, in contrast, analyze the step response of the filter. These known methods require the generation of a test signal (either on-chip or off-chip), applying the test signal at the input of the circuit under test (CUT), and reading and processing the response of the circuit. This can be done either on-chip or off-chip. For tuning purposes, the response of the filter is used in a feedback configuration to adjust its parameters.
FIGS. 1-5 are block diagrams showing circuit configurations of conventional checking methods. FIG. 1 is a block diagram showing a testing circuit 100 for an integrated filter with an external test signal source 105 and an external generic analyzer 145. As shown in FIG. 1, the testing circuit 100 includes an input buffer 110 coupled to the output of external test signal source 105, a circuit under test (CUT) 115, an output buffer 140 that provides an output to external analyzer 145, first switch 130 connected between input buffer 110 and CUT 115, second switch 135 connected between CUT 115 and output buffer 140, and an internal circuit 120 connected to receive a signal from second switch 135 and to provide a signal to first switch 130. In this circuit, input buffer 110, CUT 115, internal circuit 120, first and second switches 130 and 135, and output buffer 140 are all formed on a semiconductor chip 150, while the external test signal source 105 and the external analyzer 145 are formed off the chip 150.
The CUT 115 can be connected through the first and second switches 130 and 135 either to the internal circuit 120, or to the input and output buffers 110 and 140. When connected to input and output buffers 110 and 140 by first and second switches 130 and 135, CUT 115 is connected to the external test signal source 105 and the external analyzer 145. The first and second switches are controlled by switching signals SW. The switching signals SW indicate either a normal operation state (connecting the switches 130 and 135 to normal nodes N), or a test operation state (connecting the switches 130 and 135 to test nodes T).
FIG. 2 is a block diagram showing a testing circuit 200 for an integrated filter that is similar to the circuit shown in FIG. 1. However, an external analog-to-digital converter (ADC) 255 and digital signal processor (DSP) 260 are included in place of external analyzer 145 of FIG. 1. The testing circuit 200 of FIG. 2 is thus similar to the testing circuit 100 of FIG. 1, but the analyzer device is DSP-based. In this circuit shown in FIG. 2, input buffer 110, CUT 115, internal circuit 120, first and second switches 130 and 135, and output buffer 140 are all formed on a semiconductor chip 250, while the external test signal source 105, the external ADC 255, and the external DSP 260 are formed off chip 250. The external ADC 255 of the testing circuit 200 acts as the interface between the CUT 115 and the DSP 260. Since the ADC 255 is external, it can also be used for other functions external to the chip 250.
FIG. 3 is a block diagram showing a testing circuit 300 for an integrated filter that is similar to the circuit shown in FIG. 2. However, an internal ADC 355 is provided on the semiconductor chip 350, in place of output buffer 140 of FIG. 2. Also, external ADC 255 of FIG. 2 is not included in the circuit as shown in FIG. 3. The internal ADC 355 is coupled to receive an output from second switch 135 and provides an output directly to external DSP 260. Internal ADC 355 is dedicated to test/tuning purposes. In this circuit as shown in FIG. 3, input buffer 110, CUT 115, internal circuit 120, first and second switches 130 and 135, and internal ADC 355 are all formed on semiconductor chip 350, while the external test signal source 105 and the external DSP 260 are formed off chip 350. Since the internal ADC 355 is disposed on semiconductor chip 350, there is no need for an analog output buffer on chip 350 for testing the CUT 115. In operation, the chip 350 receives an analog test signal, and outputs a digital test signal.
FIG. 4 is a block diagram showing a testing circuit 400 for an integrated filter that is similar to the circuit shown in FIG. 3. However, internal test signal source 405 is provided on semiconductor chip 450, in place of external test signal source 105 of FIG. 3. Internal test signal source 405 provides a test signal directly to first switch 130. Input buffer 110 of FIG. 3 is not included in the circuit as shown in FIG. 4. Also, an internal DSP 460 is provided on chip 450, in place of external DSP 260 of FIG. 3. Internal DSP 460 directly receives an output of internal ADC 355. Internal DSP 460 is dedicated to test/tuning purposes. In this circuit as shown in FIG. 4, internal test signal source 405, CUT 115, internal circuit 120, first and second switches 130 and 135, internal ADC 355, and internal DSP 460 are all formed on semiconductor chip 450. Since the signal source 405 and the ADC 355 are both internal, there is no need for input and output buffers on chip 450 for testing the CUT 115. In operation, chip 450 generates input signals internally, and outputs a digital signal.
FIG. 5 is a block diagram showing a testing circuit 500 for an integrated filter that is similar to the circuit shown in FIG. 4. However, CUT 115 and internal ADC 555 are formed on main circuit 570. In other words, the internal ADC 355 of FIG. 4 is moved to be part of main circuit 570 as shown in FIG. 5. Internal ADC 555 receives an output directly from CUT 115, and provides an output to second switch 135. As previously, CUT 115 receives an input from first switch 130. In the circuit of FIG. 5, the internal ADC 555 is part of main circuit 570, and is shared as for normal operation with internal circuit 120 and as for test/tuning. In this circuit of FIG. 5, internal test signal source 405, main circuit 570, internal circuit 120, first and second switches 130 and 135, and internal DSP 460 are all formed on semiconductor chip 550.
In the testing circuit 500 of FIG. 5, internal ADC 555 is part of main circuit 570, and operates with CUT 115 during normal operation. In other words, when the switch signals SW indicate a normal mode (i.e., connecting the switches 130 and 135 to the normal nodes N), the internal circuit 120 is connected to both internal ADC 555 and CUT 115, so that internal circuit 120 uses internal ADC 555 during normal operation.
However, providing an external high-frequency test signal to a chip and channeling the external high-frequency test signal to the input of CUT 115 as in FIGS. 1-3, is an operation prone to errors because of parasitic elements, noise, DC offset and non-linear behavior of interface blocks. Extracting the response of the circuit requires interface blocks that must be able to drive external pads while keeping the loading of the CUT 115 at a minimum.
On the other hand, generating a high-frequency test/tuning signal on-chip as in FIGS. 4 and 5 requires special circuitry, such as a low-noise, accurately controlled amplitude sinusoidal oscillator. Furthermore, reading of the high-frequency response on-chip requires either special analog blocks such as precision amplitude discriminators, or an on-chip high-speed analog-to-digital converter (ADC) as well as on-chip or off-chip digital signal processing (DSP) capabilities. In the latter case, high-speed digital communication with the external test equipment is required.
It is therefore desirable to provide an easier to implement method of testing the transfer characteristic of a high-frequency integrated continuous-time filter.
The present invention is therefore directed to a transconductance-capacitance filter, and a method of verifying the transfer characteristics of a high-frequency integrated continuous-time filter of a tranconductance-capacitance type, that substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
It is thus an object of the present invention to overcome or at least minimize the various drawbacks associated with conventional techniques for testing the transfer characteristic of a high-frequency integrated continuous-time filter.
In accordance with this invention, a transconductance-capacitance integrator is provided that includes a plurality of transconductors that provide transconductor output currents; a current follower that provides an output current; a capacitor, coupled to the current follower, that provides an output voltage of the transconductance-capacitance integrator responsive to the output current; a scaling circuit that scales the transconductor output currents of the plurality of transconductors by a same scaling factor to provide a scaled transconductor output current; and a mode switch that is operable in a test/tuning operation mode to provide the scaled transconductor output current to the current follower and in a normal operation mode to provide the transconductor output current to the current follower.
The transconductors preferably have a first transconductance in the normal operation mode, and have a second transconductance in the test/tuning operation mode. In this case, the second transconductance may be obtained by dividing the output currents of the transconductors.
In test/tuning mode, the output currents of all of the transconductors may be divided by the same ratio.
The second transconductances may be obtained by dividing the output currents of the transconductors through resistive dividers.
Also in accordance with this invention, a method of verifying a transfer function of a tranconductance-capacitance filter including a plurality of transconductors that provide transconductor output currents, includes converting the transconductor output currents into a first set of output voltages during a normal operation mode of the transconductance-capacitance filter; and scaling the transconductor output currents by a scaling factor to provide a set of scaled transconductor output currents and converting the set of scaled transconductor output currents into a second set of output voltages for verifying the transfer function, during a test/tuning operation mode of the transconductance-capacitance filter.
Also in further accordance with this invention, a direct on-chip closed loop tuning system includes a first filter having a plurality of first transconductors that provide a first set of transconductor currents, a first set of adders that add the first transconductor currents to provide a first set of transconductor output currents and a first set of scalers that scale the set of first transconductor output currents to provide a set of scaled first transconductor output currents, the first filter being operable in a normal operation mode to output a first set of first transconductor output currents and in a test/tuning operation mode to output a set of scaled first transconductor output currents; a second filter having a plurality of second transconductors that provide a second set of transconductor currents, a second set of adders that add the second set of transconductor currents to provide a set of second transconductor output currents and a second set of scalers that scale the second set of transconductor output currents to provide a scaled second set of transconductor output currents, the second filter being operable in the normal operation mode to output a set of second transconductor output currents and in the test/tuning operation mode to output the scaled set of second transconductor output currents; and a controller that simultaneously switches one of the first and second filters into the normal operation mode and another of the first and second filters into the test/tuning operation mode.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.